In integrated circuits, in particular dynamic random access memories (DRAM memories), capacitors are generally used for storing charge. A DRAM memory cell is composed of a selection transistor and a storage capacitor, the information items being stored in the storage capacitor in the form of electrical charges. In this case, a DRAM memory has a matrix of such DRAM memory cells which are connected up in the form of rows and columns. The row connections are usually referred to as word lines, and the column connections as bit lines. The selection transistor and the storage capacitor in the individual DRAM memory cells are in this case connected to one another such that, in the event of the selection transistor being driven via a word line, the charge of the storage capacitor can be read in and out via a bit line.
A main focus in the technological development of DRAM memory cells is the storage capacitor. A storage capacitance of 20 to 50 fF is necessary in order to obtain a sufficient read signal. In order to achieve such a storage capacitance in the context of a continually decreasing cell area of the DRAM memory cell, use is made of so-called trench capacitors which utilize the third dimension. Trench capacitors are usually fabricated such that deep trenches are etched into the semiconductor substrate and are then filled with a dielectric layer and a first capacitor electrode, the so-called storage electrode. In this case, the storage electrode is generally an n+-doped polysilicon filling. Furthermore, a second capacitor electrode, also referred to as a buried plate, is formed in the semiconductor substrate e.g. by outdiffusion of n-type doping atoms of a dopant source around the lower section of the trench.
The selection transistor of the DRAM memory cell is then usually produced as a planar field-effect transistor beside the trench capacitor. The selection transistor has two highly doped diffusion regions, which form the source-drain electrodes and are separated by a channel region, one diffusion region being connected to the bit line of the DRAM memory cell. By contrast, the other diffusion region is connected to the storage electrode via a capacitor connection region, the so-called buried strap. The channel of the selection transistor is furthermore isolated by means of a gate dielectric layer from a gate electrode layer connected to the word line of the DRAM memory cell.
A read-in and read-out operation of the DRAM memory cell is controlled by the word line such that, as a result of the application of a voltage to the gate electrode layer, a current-conducting channel is produced between the source/drain electrodes of the selection transistor, so that information in the form of charge can be read into and out of the storage electrode via the buried strap contact.
The buried strap contact between the storage electrode and the source/drain electrode is generally fabricated such that the n+-type polysilicon filling, which is surrounded by an insulator layer, generally an SiO2 layer, in the upper trench region, is etched back into the trench. Afterward, the uncovered insulator layer is then removed from the trench wall and an n+-type polysilicon deposition of the trench is then performed again in order to fabricate a contact area between the n+-type polysilicon filling of the storage electrode and the adjoining semiconductor substrate, in which the diffusion regions of the selection transistor are subsequently embodied. After the removal of the uncovered insulator layer at the trench wall and before the filling with the n+-type polysilicon in order to form the buried strap contact, a thin liner layer, preferably Si3N4, is applied. Said liner layer serves as a barrier layer in order to prevent the n+-type polysilicon from coming into contact with the monocrystalline substrate during the filling of the buried strap contact, which would lead to undesirable recrystallization of and thus damage to the semiconductor substrate, which would then provide for a high resistance in this region that is utilized as a diffusion zone for the selection transistor. In this case, however, the liner layer in turn is thin enough to enable tunneling of charge carriers and thus an exchange of charge between the storage electrode and the source/drain electrode of the selection transistor via the buried strap contact.
The contact resistance between the storage electrode of the trench capacitor and the adjoining diffusion zone of the selection transistor constitutes an ever greater problem, however, on account of the increasing structural miniaturization. Since the previous process control means that, during the formation of the buried strap contact, the liner layer is also inevitably formed between the buried strap contact and the storage electrode, the contact resistance is very high on account of the intervening liner layer, particularly at low temperatures of −10° C. or less. In previous generations of DRAM memory cells, this contact resistance was still acceptable owing to the low speed requirements and the large cross section of the buried strap contact in the region of the trench capacitor. In the context of the further increasing constriction of the upper region of the trench capacitor and thus of the cross section of the buried strap contact, there is the risk, however, that enough charge will no longer be able to flow into the trench capacitor, which may lead to a failure of the DRAM memory cell.